1. Field of the Invention
This disclosure relates generally to semiconductor device fabrication technology and, more particularly, to a method of forming a self-aligned contact in fabricating a semiconductor device such as a memory device.
2. Description of the Related Art
As semiconductor devices becomes increasingly integrated and design rules are reduced, semiconductor fabrication technology encounters a variety of difficulties in forming circuit patterns. One such difficulty arises during the process of forming a storage node contact in a dynamic random access memory (DRAM). The storage node contact connects a storage electrode and a source region. When the storage node contact is formed in a self-aligned manner, the storage node contact may often be short-circuited with an underlying bit line. Furthermore, forming the storage node contact in such a self-aligned manner may increase the contact resistance. Increasing the thickness of a bit line mask and a bit line spacer may be favorable for the formation of the self-aligned contact. This may, however, cause voids when filling a gap between the bit lines.
A conventional method of forming the self-aligned contact is described hereinafter with reference to FIGS. 1–13. FIGS. 1 through 6 show a conventional method of fabricating the semiconductor device, and FIGS. 7 through 13 show a conventional method of forming the self-aligned contact. FIGS. 1 through 6 are plan views, and FIGS. 7 through 13 are cross-sectional views taken along the line A—A in FIG. 6, namely, in a word line direction.
Referring to FIG. 1, an isolation region 12 is formed in a semiconductor substrate (10 in FIG. 7), and thereby a number of active regions 14 are defined and surrounded by the isolation region 12. Next, as shown in FIGS. 2 and 3, word lines 16 (i.e., gate lines) and contact pads 18 and 20 are formed sequentially. Contact pad 18 is for a bit line contact that will connect a bit line and a drain region, and contact pad 20 for a storage node contact that will connect a storage electrode and a source region. The bit line contact and the storage node contact are also referred to as a direct contact (DC) and a buried contact (BC), respectively.
Next, a first interlayer dielectric layer (22 in FIG. 7) is formed to cover the resultant structure. As shown in FIG. 4, bit line contacts 24 are selectively formed in the first interlayer dielectric layer and extend downward to touch the bit line contact pads 18. Thereafter, as shown in FIGS. 5 and 6, bit lines 34 and storage node contacts 50 are formed sequentially.
The conventional method described above reaches its limits for design rules of 0.1 μm or less. In particular, the process of forming the storage node contact 50 becomes critical. The following is a detailed description from a step of forming the bit lines 34 through a step of forming the storage node contact 50.
Referring to FIG. 7, a barrier metal layer 26 is deposited on the first interlayer dielectric layer 22, and then a conductive layer 28 for the bit lines and a mask layer 30 are deposited in sequence thereon. Next, a first photoresist pattern 32 is formed on the mask layer 30. The conductive layer 28 for the bit lines is made of tungsten, for example, and the mask layer 30 is made of silicon nitride, for example.
While the first photoresist pattern 32 is used as a mask, the mask layer 30 is selectively etched as shown in FIG. 8. The first photoresist pattern 32 is then removed. Furthermore, by using the patterned mask layer 30 as a mask, the conductive layer 28 and the barrier metal layer 26 are selectively etched in sequence, thus producing the bit lines 34. In this step, because the mask layer 30 is used as an etch mask, upper portions of the mask layer 30 are damaged to several hundreds of angstroms (Å) by etching. To compensate in advance for this loss, the mask layer 30 should be deposited to a thickness of about 3000 Å or more. If not, the conductive layer 26 will be undesirably exposed in a subsequent etching step. After the bit lines 34 are formed, as shown in FIG. 9, a spacer 36 of silicon nitride may be formed on sidewalls of the bit lines 34 to protect the conductive layer 28.
The above-discussed process for forming the bit lines 34 may invite a high aspect ratio of a gap 38 between the adjacent bit lines 34. So, as shown in FIG. 10, voids 42 may be formed due to a high aspect ratio of the gap 38 when the gap 38 is filled with a second interlayer dielectric layer 40.
The second interlayer dielectric layer 40 is planarized and then, as shown in FIG. 11, a second photoresist pattern 44 is formed thereon. Thereafter, as shown in FIG. 12, the second and first interlayer dielectric layers 40 and 22 are selectively etched in sequence through the second photoresist pattern 44, and thereby contact holes 46 for the storage node contacts are produced between the bit lines 34. The second photoresist pattern 44 is then removed. In this step, an etching process of both the interlayer dielectric layers 40 and 22 is performed using the silicon nitride layer 30 as a mask, namely, in a self-aligned manner, until the storage node contact pad 20 is exposed.
The silicon nitride of the mask layer 30 has an inadequate etch selectivity to oxidize the second interlayer dielectric layer 40. So, while the contact hole 46 is formed in a self-aligned manner, an upper shoulder of the bit line 34 is attacked and narrowed, as indicated by the reference numeral 48. This may cause an unfavorable short circuit between the bit line 34 and the storage node contact 50 when the contact hole 46 is filled with conductive material, such as doped polysilicon, to form the storage node contact 50, as shown in FIG. 13.
Embodiments of the invention address these and other disadvantages of the conventional art.